1. Field of the Invention
The present invention relates to wordlines, and in particular to methods of reducing wordline sheet resistance.
2. Description of the Related Art
In a typical flash or EEPROM memory array, the memory cells are arranged in a rectangular array of rows and columns to form intersections at which there are disposed memory cell transistors. The drain of each transistor is connected to a corresponding bit line, the source of each transistor is connected to an array source voltage by an array source line, and the gate of each transistor is connected to a wordline.
Tungsten has been used for wordline applications in semiconductor memory. However, the associated sheet resistance is conventionally not as low as may be desired for certain applications.